Call for papers

The slowdown of technology scaling has shifted computer architecture toward heterogeneous, domain-specific systems. Modern SoCs increasingly combine custom accelerators with specialized interconnects, peripherals, and sensing components to meet demanding performance, efficiency, and real-time requirements. Open hardware and software ecosystems are accelerating this transition by enabling transparent design reuse, rapid prototyping, and reproducible validation.

A common strategy to manage SoC complexity is hierarchical development: critical blocks are built in-house at RTL, others are generated with HLS, and highly specialized IP is integrated from third parties. While effective for productivity, this approach makes system integration the key bottleneck. Integration errors, weak specifications, and limited system-level verification can introduce serious security, safety, and performance risks, especially in mission-critical deployments.

This workshop focuses on methods, tools, and early-stage ideas that improve trustworthy integration of next-generation heterogeneous SoCs using open platforms. We explicitly welcome AI-enabled approaches, including LLM-assisted design-space exploration, specification mining, IP integration support, verification/test generation, and security analysis. The goal is to advance open, safe, and high-performance SoC development through collaborative research and practical experimentation. The topics for the workshop include, but are not limited to:

• Security verification for hardware designs and system architectures
• Architectural aspects of secure system integration
• Secure system integration of third-party hardware components
• Automated firmware generation supporting secure system execution
• Security aspects of reconfigurable designs
• Time-predictable system execution in open-hardware designs
• Performance analysis, timing analysis, and worst-case analysis supporting time-predictable system execution and/or communications in open-hardware designs
• Automated firmware generation supporting time-predictable execution
• Fault tolerance and execution in harsh conditions leveraging open-hardware designs
• AI-driven security verification and anomaly detection in hardware and system architectures
• Machine learning methods for predictive fault analysis and threat detection in integrated systems
• Use of AI to automate detection of vulnerabilities in third-party or reconfigurable components
• AI-assisted timing and performance verification to ensure secure and predictable execution in heterogeneous architectures

Workshop format

The workshop will include the following three types of contributions:

• Submissions of 4-page (IEEE Conference format) workshop papers, which will be peer-reviewed by the workshop’s technical program committee. Accepted papers will be presented with an envisioned time slot of 15 minutes (including the Q&A). Shorter submissions are also welcome.
• Invited talks from expert speakers from both academia and industry, with slots of 30-45 minutes, depending on the number of talks.
• An open discussion that will include experts both from academia and industry as well as the workshop’s audience to further support the discussion and community building in the workshop.

We plan for a half-day workshop.