Call for papers

The diminishing returns of technology scaling on performance have paved the way for innovation in computer architecture towards heterogeneous, domain-specific architectures. Modern systems increasingly comprise domain-specific accelerators as well as specialized system components (buses, network-on-chip, peripherals, sensors, etc..) to efficiently handle the complex and computationally demanding workloads.

A popular approach to reduce the SoC design complexity involves a hierarchical strategy of differentiating the system design effort for the components of the heterogeneous architecture. This includes: (i) expensive in-house RTL development for the most critical modules, (ii) leveraging the most recent high-level synthesis (HLS) tools, and/or (iii) outsourcing highly-specialized third-party intellectual property (IP) modules to reduce cost and development time.

Despite its benefits, a diversified design methodology exacerbates the system integration challenge. Furthermore, several recent works have demonstrated how non-careful system integration can lead to dangerous conditions capable of affecting the security, safety, and performance of the system. This can derive from the combination of multiple aspects involving development bugs, lack of specifications, superficial verifications of the behavior of the IP components at the system level, and scarcity of mechanisms supporting the safe and secure system execution.

Such challenges require novel approaches in the design and verification process, in particular when dealing with the strict safety and security requirements of mission-critical systems. The research community can have a disruptive role in facing these challenges – the availability of the full codebase of multiple mature open hardware architectures and reconfigurable platforms represents an unprecedented opportunity for the development, testing, and native integration of novel mechanisms, tools, and analysis supporting security, safety, and performance efficiency for the development of the next-generation of systems.

This workshop welcomes work-in-progress contributions and novel directions to tackle the challenges and profit from the opportunities provided by open hardware designs and architectures for the development of next-generation heterogeneous SoCs. The topics for the workshop include, but are not limited to:

• Security verification for hardware designs and system architectures
• Architectural aspects of secure system integration
• Secure system integration of third-party hardware components
• Automated firmware generation supporting secure system execution
• Security aspects of reconfigurable designs
• Time-predictable system execution in open-hardware designs●
• Performance analysis, timing analysis, and worst-case analysis supporting
• time-predictable system execution and/or communications in open-hardware designs
• Automated firmware generation supporting time-predictable execution
• Fault tolerance and execution in harsh conditions leveraging open-hardware designs
• System architectures and methodologies supporting energy efficient/performant system execution in open-hardware designs
• Hardware/software co-design, co-integration and co-verification of open-source processors, accelerators, and components
• Open architectures for reconfigurable platforms and open CAD tools
• Tools and analysis for open FPGAs and reconfigurable platforms

Workshop format

The workshop will include the following three types of contributions:

• Submissions of 4-page (IEEE Conference format) workshop papers, which will be peer-reviewed by the workshop’s technical program committee. Accepted papers will be presented with an envisioned time slot of 15 minutes (including the Q&A). Shorter submissions are also welcome.
• Invited talks from expert speakers from both academia and industry, with slots of 30-45 minutes, depending on the number of talks.
• An open discussion that will include experts both from academia and industry as well as the workshop’s audience to further support the discussion and community building in the workshop.

We plan for an 8 hours workshop.